The approach used in building integrated circuits on monolithic pieces of silicon involves the fabrication of successive layers of insulating, conducting, and semiconducting materials. Each layer is patterned to form a structure that performs a specific function, usually linked with surrounding areas and subsequent layers. One of the last layers put on the wafer is a final metal layer which will extend to bonding pads which will ultimately connect the chip circuitry to external devices, such as input or output devices.
Following the patterning of this final metal layer, a passivation layer is deposited over the entire top surface of the wafer. The passivation layer is an insulating and protective layer which prevents mechanical and chemical damage during assembly and packaging. The passivation layer will be finally masked and etched to define patterns corresponding to the bonding regions in which electrical contact to the finished circuit will be made.
The passivation layer preferably provides several attributes. For example, the passivation layer should be impermeable to moisture and sodium atoms, and other highly mobile impurities. It should adhere well to the conductive metal runners as well as to the dielectric layer therebeneath. It should provide scratch protection to the underlying circuits, with thicker passivation layers generally providing greater protection. As well, it should exhibit low stress and have thermal expansion/contraction properties somewhat aligned with the underlying metal and upper interlevel dielectric. Passivation layers typically comprise one or more of doped SiO.sub.2, spin-on glass (SOG), silicon nitride, oxynitride, and combinations thereof. Passivation technology is described generally in S. Wolf, "Silicon Processing for the VLSI Era" Vol. 2--Process Integration, Lattice Press, Sun Beach, Calif., pp. 273-76, 1990, which is hereby incorporated by reference.
Predominant prior art passivation techniques are described with reference to FIGS. 1-4 of this disclosure. FIG. 1 illustrates a common technique utilizing a two-layer stack of phosphorus doped silicon dioxide overlaid with silicon nitride. Specifically, FIG. 1 illustrates a semiconductor wafer 10 having a bulk substrate region 11, field oxide regions 12, interlevel conductive runners 14, and an interlevel isolating dielectric layer 16. A metal layer has been applied and patterned atop layer 16 to define a series of projecting conductive metal runners 18. Thereafter, a thin phosphorus doped layer 20 of SiO.sub.2 is applied over layer 16 and runners 18. A thicker nitride layer 22 (typically Si.sub.3 N.sub.4) is applied atop layer 20. Finally, a layer 24 of an organic/plastic-like material such as polyimide is applied atop layer 22 to further encapsulate the wafer.
One goal in providing passivation is to provide an overall thin layer to minimize thermal expansion differences between the passivation layer(s) and underlying metal and dielectric. However, this "thin layer" objective competes with the desire to create a thick passivation layer to provide greater scratch or other damage protection.
SiO.sub.2 in the described and illustrated example is applied first as it is a very good insulator (low dielectric constant) having hardness/thermal expansion properties which closely match those of the underlying substrate materials. However, SiO.sub.2 is a poor moisture and Na barrier. Si.sub.3 N.sub.4 on the other hand is an excellent mechanical protection, chemical diffusion barrier, and moisture barrier material, but has film stress properties which can be detrimental to the metallization layers. Additionally, the Si.sub.3 N.sub.4 has a high dielectric constant which makes it a rather poor choice due to cross-talk between metal lines. Even in the depicted FIG. 1 construction, the Si.sub.3 N.sub.4 in part because of the thinness of the SiO.sub.2 layer has a large effect on the metal line to metal line capacitance and deteriorates the electrical performance of the circuit. Additionally, the gaps between metal lines 18 which include dielectric material 24 provides an additional adverse effect of a variable dielectric constant depending upon the amount of moisture within material 24. This has been shown to cause bake recoverable failures of such chips.
Further, the existing construction creates vertical and other steeply angled surfaces which can generate cracks in the dielectric or even in the bulk substrate 11 caused by forces exerted by the finished package. Such is illustrated by FIGS. 2 and 3. FIG. 2 is an enlarged view of a single one of runners 18 illustrated in FIG. 1. As illustrated, sharp jagged corners 25 are generated adjacent opposite sides of runners 18. In operation or over time due in large part to the differences in thermal expansion properties of the various materials, movement and distortion of the various materials can cause cracks 30 (FIG. 3). As illustrated, the action can tend to distort or pull the metals to one side or the other. The cracks 30 which result can expose the metal and other underlying materials to the atmosphere and moisture which can lead to destruction of the circuit. Further, angled or vertical surfaces 26 are detrimental causing the encapsulation material to "bind" on these angled protrusions 26 during expansion or contraction and generate stresses and cracks in the dielectric, metal, and substrate.
One prior art method of overcoming some of these problems includes a technique utilizing SOG (spin on glass). Such is described with reference to FIG. 4. There illustrated is the upper portion of a wafer 40 having an interlevel dielectric layer 42 with patterned metal runners 44 positioned thereatop. A layer 46 of phosphorus doped SiO.sub.2 is applied atop layer 42 and runners 44. Thereafter, a layer 48 of SOG is applied. SOG has a tendency to be less conformal providing greater coverage or material in the voids between runners 44 than on the area atop runners 44. Consequently although jagged corners 25 remain with respect to the applied layer of SiO.sub.2, the effect of such corners are passivated somewhat by the more gradual sloping of SOG layer applied thereatop. After application of SOG layer 48, a layer 50 of Si.sub.3 N.sub.4 is applied, followed by a plastic/organic layer 52. Although this technique alleviates some of the problems, SOG is not without inherent drawbacks. Even though SOG is predominantly SiO.sub.2, SOG does not provide as dense a coating as pure SiO.sub.2 or boron and/or phosphorus doped SiO.sub.2 (BPSG). Further, SOG is very porous and contains undesirable impurities. In addition, the angled protrusions 26 are still present.
It is an object of the invention to overcome many of the above and additional drawbacks associated with present passivation techniques.